PROJECTS & RESEARCH
Selected academic projects in RTL design, circuit design, and hardware acceleration.
OAI333 Logic Design and Analysis (Static vs Dynamic Logic)
Transistor-level OAI333 gate designed and verified in both static CMOS and dynamic logic styles — schematic capture, DRC/LVS-clean layout, post-layout extraction, and timing validation in Cadence Virtuoso.
Transistor-level OAI333 gate designed and verified in both static CMOS and dynamic logic styles — schematic capture, DRC/LVS-clean layout, post-layout extraction, and timing validation in Cadence Virtuoso. Power, delay, and variability analysis via 100-run Monte Carlo simulations, benchmarking trade-offs in robustness, area, and performance.
Two-Stage CMOS Operational Amplifier
Designed and simulated a two-stage CMOS op-amp in Cadence Virtuoso: ~60 dB DC gain, ~5 MHz gain-bandwidth product, >60° phase margin, 1.8–2.5V supply.
Designed and simulated a two-stage CMOS op-amp in Cadence Virtuoso: ~60 dB DC gain, ~5 MHz gain-bandwidth product, >60° phase margin, 1.8–2.5V supply. Validated slew rate >5 V/µs at 100 µA tail current through AC, transient, and power analysis; evaluated ICMR, output swing, stability, and power dissipation.
Neural Networks using Magnetic Tunnel Junctions (MTJ) for Neuromorphic Computing
Researched MTJ-based neuromorphic architectures — crossbar in-memory neural network acceleration, stochastic switching behavior, quantized weight storage, and energy-efficient ANN/CNN hardware mapping.
Researched MTJ-based neuromorphic architectures — crossbar in-memory neural network acceleration, stochastic switching behavior, quantized weight storage, and energy-efficient ANN/CNN hardware mapping. Evaluated quantized neural network performance on MNIST, Fashion-MNIST, and CIFAR-10, reaching up to 97.64% ANN accuracy and ~70.52% retrained CNN accuracy post-discretization. Studied MTJ reliability and BER-energy trade-offs.